Electrostatic discharge (ESD) protection is conventionally provided at the bond pads or adjacent input and output lines of integrated circuit devices to protect input and output transistors from ESD spike voltages exceeding the dielectric breakdown voltage of input and output transistors. The dielectric breakdown voltage for the gate oxide layer which provides the channel insulating layer for MOS transistors is typically in the range of 15 volts. During handling of IC devices, the bond pads coupled to the outside world may receive electrostatic discharges causing positive and negative transient voltage spikes greatly exceeding this dielectric breakdown voltage. A characteristic of the voltage spikes from ESD events is the fast rise time for example in the order of 5nS to 15nS while normal power up and power down events in the power rails are typically in the order of microseconds.
A variety of ESD protection circuit arrangements have been devised for diverting to the respective power rails ESD voltages appearing at the bond pads and adjacent input and output lines. A simplified ESD protection circuit is provided for example by clamping the input or output line at the respective bond pad using ESDP diodes. For example current flow is oriented from the bond pad through a first diode to the high potential power rail for ESD events at the bond pad exceeding the voltage VCC on the high potential power rail. A second ESDP diode is oriented for current flow from ground to the bond pad for negative voltage spikes.
Further background on ESD protection is discussed for example, in the Jeffrey B. Davis and Stephen C. Park U.S. patent application Ser. No. 08/122,120, filed Sep. 16, 1993 for ELECTROSTATIC DISCHARGE PROTECTION TRANSISTOR ELEMENT FABRICATION PROCESS. Davis et al. describe an electrostatic discharge protection transistor element also used for clamping an input or output line of an IC device for diverting ESD voltages before occurrence of dielectric breakdown voltages at the internal transistor elements. The Davis et al. ESDP transistor solves other problems caused by clamping diodes during power up and power down of an IC device.
Variations on similar ESD protection circuits are described in the Huard U.S. Pat. No. 4,875,130 issued Oct. 17, 1989 for ESD LOW RESISTANCE INPUT STRUCTURE. A BICMOS ESD protection circuit is described in the James R. Ohannes et al. U.S. patent application Ser. No. 07/839,825 filed Feb. 21, 1992 for BICMOS ESDP CIRCUIT.
A more elaborate ESD protection circuit for use at the input or output lines adjacent to bond pads is illustrated in FIG. 1. This circuit is described in the Stephen W. Clukey U.S. patent application Ser. No. 08/184,261 filed Jan. 21, 1994 for MULTIRAIL ESDP DEVICE. For ESD protection the circuit of FIG. 1 uses three bipolar transistors QA, QB, QC with emitters coupled respectively to the input line to be protected, the high potential power rail VCC, and the low potential power rail GND. The respective collector nodes of the three bipolar transistors QA, QB, QC are coupled together at a common node. By this Y network arrangement the voltage path in any direction across the network is equal to VEC+VCE. With the bases of the bipolar transistors floating, the breakdown voltage across any path of the Y network is approximately 10 volts. This permits diversion of both positive and negative ESD voltages before the ESD voltage can rise above the dielectric breakdown voltage of internal MOS transistors. A diode connected Schottky transistor can also be coupled between the input line to be protected and ground for further protection from negative voltage spikes.
While the foregoing circuits can provide bond pad protection to input and output transistors for ESD events up to the standard of 2000 volts and even greater, e.g. up to 4000 volts, a further difficulty has been encountered in more recent BICMOS circuits that incorporate both bipolar technology and MOS technology. Specifically during ESD testing there is consistent failure of internal NMOS pulldown transistors that are coupled to bipolar emitter follower pullup transistors. During ESD events the N channel transistors breakdown because of the voltage across the source and drain and the low impedance bipolar emitter followers used as pullup transistors source sufficient current to fuse the source and drain of the N channel transistors. This problem encountered with BICMOS technology is not resolved by the conventional ESD protection circuits at the bond pad input and output lines.